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octal, 12-/16-bit nano dac+ with 2 ppm/c reference, i 2 c interface data sheet ad5671r / ad5675r rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014C2015 analog devices, inc. all rights reserved. technical support www.analog.com features high performance high relative accuracy (inl): 3 lsb maximum at 16 bits total unadjusted error (tue): 0.14% of fsr maximum offset error: 1.5 mv maximum gain error: 0.06% of fsr maximum low drift 2.5 v reference: 2 ppm/c typical wide operating ranges ?40c to +125c temperature range 2.7 v to 5.5 v power supply easy implementation user selectable gain of 1 or 2 (gain pin/bit) 1.8 v logic compatibility 400 khz i 2 c-compatible serial interface robust 2 kv hbm and 1.5 kv ficdm esd rating 20-lead, rohs-compliant tssop and lfcsp applications optical transceivers base station power amplifiers process control (plc input/output cards) industrial automation data acquisition systems general description the ad5671r / ad5675r are low power, octal, 12-/16-bit buffered voltage output digital-to-analog converters (dacs). they include a 2.5 v, 2 ppm/c internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 v (gain = 1) or 5 v (gain = 2). the devices operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the ad5671r / ad5675r are available in a 20-lead tssop and in a 20-lead lfcsp and incorporate a power-on reset circuit and a rstsel pin that ensures the dac outputs power up to zero scale or midscale and remain there until a valid write. the ad5671r / ad5675r contain a power-down mode, reducing the current consumption to 1 a typical while in power-down mode. table 1. octal nano dac+? devices interface reference 16-bit 12-bit spi internal ad5676r ad5672r external ad5676 not applicable i 2 c internal ad5675r ad5671r product highlights 1. high relative accuracy (inl) ad5671r (12-bit): 1 lsb maximum ad5675r (16-bit): 3 lsb maximum 2. low drift, 2.5 v on-chip reference functional block diagram figure 1. interface logic input register a0 a1 gnd v out 7 ldac sda scl ad5671r/ad5675r reset 2.5v ref v out 0 v out 1 v out 2 v out 3 v out 4 v out 5 v out 6 dac register string dac 0 buffer input register dac register string dac 1 buffer input register dac register string dac 2 buffer input register dac register string dac 3 buffer input register dac register string dac 4 buffer input register dac register string dac 5 buffer input register dac register string dac 6 buffer input register dac register string dac 7 buffer gain power-down logic power-on reset v logic v dd v refout rstsel gain 1/2 12664-001
ad5671r/ ad5675r data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ad5671r specif ications .............................................................. 3 ad5675r specifications .............................................................. 5 ac characteristics ........................................................................ 7 timing characteristics ................................................................ 8 absolute maximum ratings ............................................................ 9 ther mal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 11 ter mi nolo g y .................................................................................... 20 theory of operation ...................................................................... 22 digital - to - analog converter (dac) ....................................... 22 transfer function ....................................................................... 22 dac architecture ....................................................................... 22 serial interface ............................................................................ 23 write and update commands .................................................. 24 i 2 c slave address ........................................................................ 24 serial operation ......................................................................... 24 write operation .......................................................................... 24 read operati on ........................................................................... 25 multiple dac readback sequence .......................................... 25 power - down operation ............................................................ 26 load dac (hardware ldac pin) ........................................... 26 ldac mask register ................................................................. 27 hardware reset ( reset ) .......................................................... 28 reset select pin (rstsel) ........................................................ 28 internal reference and amplifier gain selection .................. 28 solder heat reflow ..................................................................... 28 long - ter m temperature drift ................................................. 28 thermal hysteresis .................................................................... 29 applications information .............................................................. 30 power supply recommendations ............................................. 30 microprocessor interfacing ....................................................... 30 ad5671r/ad5675r to adsp - bf531 interface .................... 30 layout guidelines ....................................................................... 30 galvanically isolated interface ................................................. 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision history 10 /15 rev. a to rev. b added 20 - lead lfcsp ....................................................... universal change s to features section and figure 1 .................................... 1 changes to reference temperature coefficient parameter , table 2 and i logic parameter, table 2 ............................................. 3 changes to reference temperature coefficient parameter , table 3 and i logic parameter, table 3 ............................................. 5 changes t o tabl e 6 ............................................................................ 9 added thermal resistance section and table 7 ; renumbered sequentially ...................................................................................... 9 added figure 5 ; renumbered sequentially ................................ 10 changes to table 8 .......................................................................... 10 changes to termi n ology section .................................................. 20 change to table 9 ........................................................................... 23 change to read operation section .............................................. 25 changes to ldac mask register section and table 1 4 ............ 27 changed internal reference setup section to internal reference and amplier gain selection section ............................................ 28 changes to i n ternal reference and amplier gain selection (lfcsp only) section and table 16 ............................................. 28 changes to table 17 ....................................................................... 29 changes to galvanically isolated interface section and figure 70 .......................................................................................... 30 updated outline dimensions ....................................................... 31 changes to ordering guide .......................................................... 31 2/1 5 rev. 0 to rev. a added ad5671r specifications section ........................................ 3 changes to table 2 ............................................................................. 3 added ad5675r specifications section and table 3 ; renumbered sequentially ................................................................ 5 changes to table 5 ............................................................................. 8 added fig ure 3 ; renumbered sequentially ................................... 8 change to terminology section ................................................... 20 change to transfer function section .......................................... 22 changes to hardware reset ( reset ) sectio n ............................ 28 changes to ordering guide .......................................................... 31 10 /14 revision 0: initial version
data sheet ad5671r/ad5675r rev. b | page 3 of 32 specifications ad5671r specifications v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v, r l = 2 k, c l = 200 pf, all specifications t a = ?40c to +125c, unless otherwise noted. table 2. parameter min typ max unit test conditions/comments static performance 1 resolution 12 bits relative accuracy (inl) 0.12 1 lsb gain = 1 0.12 1 lsb gain = 2 differential nonlinearity (dnl) 0.01 0.1 lsb gain = 1 0.01 0.1 lsb gain = 2 zero-code error 0.8 1.6 mv gain = 1 or gain = 2 offset error ?0.75 2 mv gain = 1 ?0.1 1.5 mv gain = 2 full-scale error ?0.018 0.14 % of fsr gain = 1 ?0.013 0.07 % of fsr gain = 2 gain error +0.04 0.12 % of fsr gain = 1 ?0.02 0.06 % of fsr gain = 2 tue 0.03 0.18 % of fsr gain = 1 0.006 0.14 % of fsr gain = 2 offset error drift 2 1 v/c dc power supply rejection ratio (psrr) 2 0.25 mv/v dac code = midscale, v dd = 5 v 10% dc crosstalk 2 2 v due to single channel, full-scale output change 3 v/ma due to load current change 2 v due to powering down (per channel) output characteristics 2 output voltage range 0 2.5 v gain = 1 0 5 v gain = 2 output current drive 15 ma capacitive load stability 2 nf r l = 10 nf r l = 1 k resistive load 3 1 k load regulation 183 v/ma v dd = 5 v 10%, dac code = midscale, ?30 ma i out +30 ma 177 v/ma v dd = 3 v 10%, dac code = midscale, ?20 ma i out +20 ma short-circuit current 4 40 ma load impedance at rails 5 25 power-up time 2.5 s coming out of power-down mode, v dd = 5 v reference output output voltage 6 2.4975 2.5025 v reference temperature coefficient 7, 8 see the terminology section 20-lead tssop 2 5 ppm/c 20-lead lfcsp 5 10 ppm/c output impedance 2 0.04 output voltage noise 2 13 v p-p 0.1 hz to 10 hz output voltage noise density 2 240 nv/hz at ambient, f = 10 khz, c l = 10 nf, gain = 1 or 2 load regulation sourcing 2 29 v/ma at ambient load regulation sinking 2 74 v/ma at ambient output current load capability 2 20 ma v dd 3 v line regulation 2 43 v/v at ambient long-term stability/drift 2 12 ppm after 1000 hours at 125c thermal hysteresis 2 125 ppm first cycle 25 ppm additional cycles
ad5671r/ ad5675r data sheet rev. b | page 4 of 32 parameter min typ max unit test conditions/comments logic inputs 2 input current 1 a per pin input voltage low, v inl 0.3 v logic v high, v inh 0.7 v logic v pin capacitance 3 pf logic outputs (sda) 2 output voltage low, v ol 0.4 v i sink = 200 a high, v oh v logic ? 0.4 v i source = 200 a floating state output capacitance 4 pf power requirements v logic 1.8 5.5 v i logic 3 a power - on, ?40c + 105c 3 a power - on, ?40c + 125c 3 a power - down, ?40c + 105c 3 a power - down, ?40c + 125c v dd 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 9 1.1 1.26 ma internal reference off, ?40c to +85c 1.8 2.0 ma internal reference on, ?40c to +85c 1.1 1.3 ma internal reference off 1.8 2.1 ma internal reference on all power - down modes 10 1 1.7 a tristate to 1 k, ?40c to +85c 1 1.7 a power down to 1 k, ?40cto +85c 1 2.5 a tristate, ?40c to +105c 1 2.5 a power down to 1 k, ?40c to +105c 1 5.5 a tristate to 1 k, ?40c to +125c 1 5.5 a power down to 1 k, ?40c to +125c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1 , or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 12 to 4080 . 2 guaranteed by design and characte rization ; not production tested. 3 together, channel 0, channel 1, channel 2, and channel 3 can source/sink 40 ma. similarly, together, channel 4, channel 5, ch annel 6, and channel 7 can source/sink 40 ma up to a junction temperature of 125c. 4 v dd = 5 v . the device s include current limiting to protect the devices during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum operation junction temperature may impair device reliability . 5 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 typical channel res istance of the output devices. for example , when sinking 1 m a, the minimum output voltage = 25 1 ma = 25 mv. 6 initial accuracy presolder reflow is 750 v; o utput volta ge includes the effects of preconditioning drift. see the internal reference and amplifier gain selection section. 7 reference is trimmed and tested at two temperatures and is characteri z ed from ? 40c to +125c . 8 reference temperature coefficient calculated as per the box m ethod. see the terminology section for further information. 9 interface inactive. all dacs active. dac outputs unloaded. 10 all dacs powered down.
data sheet ad5671r/ad5675r rev. b | page 5 of 32 ad5675r specifications v dd = 2.7 v to 5.5 v , 1.8 v v logic 5.5 v , r l = 2 k?, c l = 200 pf, a ll specifications t a = ?40c to +125c , unless otherwise noted. table 3. a grade b grade parameter min typ max min typ max unit test conditions/comments static performance 1 resolution 16 16 bits relative accuracy (inl) 1.8 8 1.8 3 lsb gain = 1 1.7 8 1.7 3 lsb gain = 2 differential nonlinearity (dnl) 0.7 1 0.7 1 lsb gain = 1 0.5 1 0.5 1 lsb gain = 2 zero - code error 0.8 4 0.8 1.6 mv gain = 1 or gain = 2 offset error ?0.75 6 ?0.75 2 mv gain = 1 ?0.1 4 ?0.1 1.5 mv gain = 2 full - scale error ?0.018 0.28 ?0.018 0.14 % of fsr gain = 1 ?0.013 0.14 ?0.013 0.07 % of fsr gain = 2 gain error +0.04 0.24 +0.04 0.12 % of fsr gain = 1 ?0.02 0.12 ?0.02 0.06 % of fsr gain = 2 tue 0.03 0.3 0.03 0.18 % of fsr gain = 1 0.006 0.25 0.006 0.14 % of fsr gain = 2 offset error drift 2 1 1 v/c dc psrr 2 0.25 0.25 mv/v dac code = midscale, v dd = 5 v 10% dc crosstalk 2 2 2 v due to single channel, full - scale output change 3 3 v/ma due to load current change 2 2 v due to powering down (per channel) output characteristics 2 output voltage range 0 2.5 0 2.5 v gain = 1 0 5 0 5 v gain = 2 output current drive 15 15 ma capacitive load stability 2 2 nf r l = 10 10 nf r l = 1 k resistive load 3 1 1 k load regulation 183 183 v/ma v dd = 5 v 10%, dac code = midscale, ?30 ma i out +30 ma 177 177 v/ma v dd = 3 v 10%, dac code = midscale, ?20 ma i out +20 ma short - circuit current 4 40 40 ma load impedance at rails 5 25 25 power - up time 2.5 2.5 s coming out of power - down mode, v dd = 5 v reference output output voltage 6 2.4975 2.5025 2.4975 2.5025 v reference temperature coefficient 7 , 8 see the terminology section 20 - lead tssop 5 20 2 5 ppm/c 20- lead lfcsp 5 20 2 10 ppm/c output impedance 2 0.04 0.04 output voltage noise 2 13 13 v p - p 0.1 hz to 10 hz output voltage noise density 2 240 240 nv/hz at ambient, f = 10 khz, c l = 10 nf, gain = 1 or 2 load regulation sourcing 2 29 29 v/ma at ambient load regulation sinking 2 74 74 v/ma at ambient output current load capability 2 20 20 ma v dd 3 v line regulation 2 43 43 v/v at ambient
ad5671r/ad5675r data sheet rev. b | page 6 of 32 a grade b grade parameter min typ max min typ max unit test conditions/comments long - term stability/drift 2 12 12 ppm after 1000 hours at 125c thermal hysteresis 2 125 125 ppm first cycle 25 25 ppm additional cycles logic inputs 2 input current 1 1 a per pin input voltage low, v inl 0.3 v logic 0.3 v logic v high, v inh 0.7 v logic 0.7 v logic v pin capacitance 3 3 pf logic outputs (sda) 2 output voltage low, v ol 0.4 0.4 v i sink = 200 a high, v oh v logic ? 0.4 v logic ? 0.4 v i source = 200 a floating state output capacitance 4 4 pf power requirements v logic 1.8 5.5 1.8 5.5 v i logic 3 3 a power - on, ?40c + 105c 3 3 a power - on, ?40c + 125c 3 3 a power - down, ?40c + 105c 3 3 a power - down, ?40c + 125c v dd 2.7 5.5 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 9 1.1 1.26 1.1 1.26 ma internal reference off, ?40c to +85c 1.8 2.0 1.8 2.0 ma internal reference on, ?40c to +85c 1.1 1.3 1.1 1.3 ma internal reference off 1.8 2.1 1.8 2.1 ma internal reference on all power - down modes 10 1 1.7 1 1.7 a tristate to 1 k , ?40c to +85c 1 1.7 1 1.7 a power down to 1 k , ?40c to +85c 1 2.5 1 2.5 a tristate, ?40c to +105c 1 2.5 1 2.5 a power down to 1 k , ?40c to +105c 1 5.5 1 5.5 a tristate to 1 k , ?40c to +125c 1 5.5 1 5.5 a power down to 1 k , ?40c to +125c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1 , or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 256 to 65 , 280. 2 guaranteed by design and characterization ; not production tested. 3 togeth er, channel 0, channel 1, channel 2, and channel 3 can source/sink 40 ma. similarly, together, channel 4, channel 5, channel 6, and channel 7 can source/sink 40 ma up to a junction temperature of 125c. 4 v dd = 5 v . the device s include current limiting to protect the devices during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum operation junction temperature may impair device reliability. 5 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 typical channel res istance of the output devices. fo r example, when sinking 1 ma, the minimum output voltage = 25 1 ma = 25 mv. 6 initial accuracy presolder reflow is 750 v; o utput voltage includes the effects of preconditioning drift. see the internal reference and amplifier gain selection section. 7 reference is trimmed and tested at two temperatures and is characteri z ed from ? 40c to +12 5c . 8 reference temperature coefficient calculated as per the box method. see the terminology section for further information. 9 interface inactive. all dacs active. dac outputs unloaded. 10 all dacs powered down.
data sheet ad5671r/ad5675r rev. b | page 7 of 32 ac characteristics v dd = 2.7 v to 5.5 v , r l = 2 k? to gnd , c l = 200 pf to gnd , 1.8 v v logic 5.5 v , all specifications t a = ?40c to +125c , unless otherwise noted. guaranteed by design and characterization; not production tested. table 4. parameter min typ max unit test conditions/comments 1 output voltage settling time 2 ad5671r 5 8 s ? to ? scale settling to 2 lsb ad5675r 5 8 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital -to - analog glitch impulse 2 1.4 nv - sec 1 lsb change around major carry (internal reference, gain = 1) digital feedthrough 2 0.13 nv - sec crosstalk 2 digital 0.1 nv - sec analog ?0.25 nv - sec ?1.3 nv - sec internal reference, gain = 2 dac - to - dac ?2.0 nv - sec internal reference, gain = 2 total harmonic distortion (thd) 3 ?80 db at t a , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density 2 300 nv/ hz dac code = midscale, 10 khz; gain = 2 output noise 2 6 v p -p 0.1 hz to 10 hz, gain = 1 signal -to - noise ratio (snr) 90 db at t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz spurious - free dynamic range (sfdr) 83 db at t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz signal -to - noise - and - distortion ratio ( sinad) 80 db at t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz 1 the operating temperature range is ?40 c to +125c; t a = 25c . 2 see the terminology section . measured using internal reference and gain = 1 , unless otherwise noted . 3 digitally generated sine wave at 1 khz.
ad5671r/ad5675r data sheet rev. b | page 8 of 32 timing characteristi cs v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v, all specifications ? 40 c to +125 c , unless otherwise noted. table 5. parameter 1 , 2 min max unit description t 1 0.92 s scl cycle time t 2 0.11 s t high , scl high time t 3 0.44 s t low , scl low time t 4 0.04 s t hd,sta , start/repeated start hold time t 5 40 ns t su,dat , data setup time t 6 3 ? 0.04 s t hd,dat , data hold time t 7 ? 0.045 s t su,sta , repeated start setup time t 8 0.195 s t su,sto , stop condition setup time t 9 0.12 s t buf , bus free time between a stop condition and a start condition t 10 4 0 ns t r , rise time of scl and sda when receiving t 11 4 , 5 20 + 0.1c b ns t f , fall time of scl and sda when transmitting/receiving t 12 20 ns ldac pulse width t 13 0.4 ns scl rising edge to ldac rising edge t 14 4.8 ns reset minimum pulse width low, 1.8 v v logic 2.7 v 6.2 ns reset minimum pulse width low, 2.7 v v logic 5.5 v t 15 132 ns reset activation time , 1.8 v v logic 2.7 v 80 ns reset activation time , 2.7 v v logic 5.5 v t sp 6 0 ns pulse width of suppressed spike c b 5 400 pf capacitive load for each bus line 1 see figure 2 . 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the minimum v ih o f the scl signal) to bridge the undefin ed region of the scl falling edge. 4 t r and t f are measured from 0.3 v dd to 0.7 v dd . 5 c b is the total capacitance of one bus line in pf . 6 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns. timing diagram s figure 2 . 2 - wire serial interface timing diagram figure 3 . reset timing diagram scl sda t 1 t 3 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 6 t 5 t 7 t 8 t 2 t 13 t 4 t 11 t 10 t 12 t 12 t 9 12664-002 reset t 14 t 15 v out x 12664-102
data sheet ad5671r/ad5675r rev. b | page 9 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v v out x to gnd ?0.3 v to v dd + 0.3 v v ref out to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v logic + 0.3 v operating temperature range ?40c to +12 5c storage temperature range ?65c to +150c junction temperature 125c reflow soldering peak temperature, pb free (j - std -020) 260c esd human body model (hbm) 2 kv field induced charged device model (ficdm) 1.5 kv stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended period s may affect product reliability. thermal resistance the design of the thermal board requires close attention. thermal resistance is highly impacted by the printed circuit board ( pcb) being used, layout, and environmental conditions. table 7 .thermal resistance package type ja jb jc jt jb unit 20- lead tssop (ru -20) 1 98.65 44.39 17.58 1.77 43.9 c/w 20- lead lfcsp (cp -20-8) 2 82 16.67 32.5 0.43 22 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51 2 thermal impedance simulated values are based on a jedec 2s2p thermal test board with nine thermal vias. see jedec jesd51. esd caution
ad5671r/ad5675r data sheet rev. b | page 10 of 32 pin configurations and function descriptions figure 4. tssop pin configuration figure 5. lfcsp pin configuration table 8. pin function descriptions pin no. mnemonic description tssop lfcsp 1 19 v out 1 analog output voltage from dac 1. the outp ut amplifier has rail-to-rail operation. 2 20 v out 0 analog output voltage from dac 0. the outp ut amplifier has rail-to-rail operation. n/a 1 0 epad exposed pad. the exposed pad must be tied to gnd. 3 1 v dd power supply input. these devices operate from 2.7 v to 5.5 v. decouple the v dd supply with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 2 v logic digital power supply. the voltage on this pin ranges from 1.8 v to 5.5 v. 5 3 scl serial clock line. in conjunction with the sda line, this pin clocks data into or o ut of the 24-bit input shift register. 6 4 a0 address input. sets the first lsb of the 7-bit slave address. 7 5 a1 address input. sets the second lsb of the 7-bit slave address. 8 gain span set pin. when this pin is tied to gnd, all eight dac outputs have a span from 0 v to v ref . if this pin is tied to v logic , all eight dacs output a span of 0 v to 2 v ref . 9 6 v out 7 analog output voltage from dac 7. the outp ut amplifier has rail-to-rail operation. 10 7 v out 6 analog output voltage from dac 6. the outp ut amplifier has rail-to-rail operation. 11 8 v out 5 analog output voltage from dac 5. the outp ut amplifier has rail-to-rail operation. 12 9 v out 4 analog output voltage from dac 4. the outp ut amplifier has rail-to-rail operation. n/a 1 10, 16 nic no internal connection. 13 11 gnd ground reference point for all circuitry on the device. 14 rstsel power-on reset pin. tie this pin to gnd to power up all eight dacs to zero scale. tie this pin to v logic to power up all eight dacs to midscale. 15 12 ldac load dac. ldac operates in two modes, asynchronously and synchronously. pulsing this pin low updates any or all dac registers if the input registers have new data, which simultaneously updates all dac outputs. this pin can also be tied permanently low. 16 13 sda serial data input. in conjunction with the scl line, this pin clocks data in to or out of the 24-bit input shift register. sda is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor. 17 14 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or midscale, depending on the state of the rstsel pin. 18 15 v refout reference output voltage. when using the internal refere nce, this is the reference output pin. this pin is the reference output by default. 19 17 v out 3 analog output voltage from dac 3. the outp ut amplifier has rail-to-rail operation. 20 18 v out 2 analog output voltage from dac 2. the outp ut amplifier has rail-to-rail operation. 1 n/a means not applicable. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v out 0 v dd v logic a1 a0 scl v out 1 v out 3 v refout reset rstsel ldac sda v out 6 v out 7 gain v out 5 v out 4 gnd v out 2 top view (not to scale) ad5671r/ ad5675r 12664-006 12664-105 14 13 12 1 3 4 reset 15 v refout sda ldac 11 gnd v dd scl 2 v logic a0 5 a1 7 v o u t 6 6 v o u t 7 8 v o u t 5 9 v o u t 4 1 0 n i c 1 9 v o u t 1 2 0 v o u t 0 1 8 v o u t 2 1 7 v o u t 3 1 6 n i c notes 1. nic = no intern a l connection. 2 . exposed pad. the exposed pad must be tied to gnd. a d5671r/ad5675r top view (not to scale)
data sheet ad5671r/ad5675r rev. b | page 11 of 32 typical performance characte risti cs figure 6 . ad5675r inl error vs. code figure 7 . ad5671r inl error vs. code figure 8 . ad5675r dnl error vs. code figure 9 . ad5671r dnl error vs. code figure 10 . ad5675r tue vs. code fi gure 11 . ad5671r tue vs. code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 10000 20000 30000 40000 50000 60000 70000 in l error (lsb) code 12664-007 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 500 1000 1500 2000 2500 3000 3500 4000 in l error (lsb) code 12664-008 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 70000 dn l error (lsb) code 12664-009 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 500 1000 1500 2000 2500 3000 3500 4000 dn l error (lsb) code 12664-010 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0 10000 20000 30000 40000 50000 60000 70000 tue (% of fsr) code 12664-0 1 1 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0 500 1000 1500 2000 2500 3000 3500 4000 tue (% of fsr) code 12664-012
ad5671r/ad5675r data sheet rev. b | page 12 of 32 figure 12 . ad5675r inl error vs. temperature figure 13 . ad5671r inl error vs. supply voltage figure 14 . ad5675r dnl error vs. temperature figure 15 . ad5671r dnl error vs. temperature figure 16 . ad5675r tue vs. temperature figure 17 . ad5671r tue vs. temperature ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 inl error (lsb) temperature (c) v dd = 5v t a = 25c internal reference = 2.5v 12664-013 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 inl error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 12664-014 ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 dn l error (lsb) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v 12664-015 ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 dn l error (lsb) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v 12664-016 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 tue (% of fsr) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v 12664-017 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 tue (% of fsr) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v 12664-018
data sheet ad5671r/ad5675r rev. b | page 13 of 32 figure 18 . ad5675r inl error vs. supply voltage figure 19 . ad5675r dnl error vs. supply voltage figure 20 . ad5671r dnl error vs. supply voltage figure 21 . ad5675r tue vs. supply voltage figure 22 . ad5671r tue vs. supply voltage figure 23 . ad5675r gain error and full - scale error vs. temperature ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 in l error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 12664-025 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 dn l error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 12664-027 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 dn l error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 12664-028 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 tue (% of fsr) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 12664-029 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 tue (% of fsr) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v 12664-030 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temper a ture (c) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 12664-031
ad5671r/ad5675r data sheet rev. b | page 14 of 32 figure 24 . ad5671r gain error and full - scale error vs. temperature figure 25 . ad5675r gain error and full - scale error vs. supply voltage figure 26 . ad5671r gain error and full - scale error vs. supply voltage figure 27 . ad5675r zero - code error and offset error vs. temperature figure 28 . ad5671r zero - code error and offset error vs. temperature figure 29 . ad5675r zero - code error and offset error vs. supply voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temper a ture (c) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 12664-032 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 error (% of fsr) supp l y vo lt age (v) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 12664-033 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 error (% of fsr) supp l y vo lt age (v) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c internal reference = 2.5v 12664-034 ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 ?40 ?20 0 20 40 60 80 100 120 error (mv) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v o ff s e t e rr o r ze r o c od e e rr o r 12664-035 ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 ?40 ?20 0 20 40 60 80 100 120 error (mv) temper a ture (c) v dd = 5v t a = 25c internal reference = 2.5v o ff s e t e rr o r ze r o c od e e rr o r 12664-036 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.7 3.2 3.7 4.2 4.7 5.2 error (mv) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v o ff s e t e rr o r ze r o c od e e rr o r 12664-037
data sheet ad5671r/ad5675r rev. b | page 15 of 32 figure 30 . ad5671r zero - code error and offset error vs. supply voltage figure 31 . supply current ( i dd ) histogram with internal reference figure 32 . headroom/footroom vs. load current figure 33 . source and sink capability at 5 v figure 34 . source and sink capability at 3 v figure 35 . supply current (i dd ) vs. code ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.7 3.2 3.7 4.2 4.7 5.2 error (mv) supp l y vo lt age (v) v dd = 5v t a = 25c internal reference = 2.5v o ff s e t e rr o r ze r o c od e e rr o r 12664-038 0 10 20 30 40 50 60 70 1700 1715 1730 1745 1760 1775 1790 1805 1820 1835 1850 1865 1880 1895 hits i dd ful l scale (a) v dd = 5v t a = 25c internal reference = 2.5v 12664-039 ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 0 0.005 0.010 0.015 0.020 0.025 0.030 v out (v) load current (a) s i n k i n g, v dd = ? 2 .7v s i n k i n g, v dd = ? 3 .0v s i n k i n g, v dd = ? 5 .0v s o u r c i n g, v dd = ?5.0v s o u r c i n g, v dd = ?3.0v s o u r c i n g, v dd = ?2.7v 12664-041 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x8000 0x4000 0x0000 0xc000 12664-042 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x0000 0x8000 0xc000 12664-043 1.0 1.1 1.2 1.3 1.4 1.5 1.6 0 10000 20000 30000 40000 50000 60000 70000 i dd (ma) code device1 device2 device3 12664-044
ad5671r/ad5675r data sheet rev. b | page 16 of 32 figure 36 . supply current (i dd ) vs. temperature figure 37 . supply current (i dd ) vs. supply voltage figure 38 . supply current (i dd ) vs. logic input voltage figure 39 . full - scale settling time figure 40 . power - o n reset to 0 v and midscale figure 41 . exiting power - down to midscale ?40 ?20 0 20 40 60 80 100 120 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i dd (ma) temper a ture (c) full-scale zero code externa l reference, full-scale 12664-045 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.7 3.2 3.7 4.2 4.7 5.2 i dd (ma) supp l y vo lt age (v) full-scale zero code externa l reference, full-scale 12664-046 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.7 3.2 3.7 4.2 4.7 5.2 supp l y vo lt age (v) zero code full-scale externa l reference, full-scale i dd (ma) 12664-047 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 v out (v) time (s) v dd = 5.5v gain = +1 internal reference = 2.5v 1/4 to 3/4 scale 12664-048 da c 1 da c 2 da c 3 da c 4 da c 5 da c 5 da c 7 da c 8 ?0.001 0 0.001 0.002 0.003 0.004 0.005 0.006 ?1 0 1 2 3 4 5 6 0 2 4 6 8 10 v out (v) v dd (v) time (ms) 12664-049 v dd (v) v out 0 (v) v out 1 (v) v out 2 (v) v out 3 (v) v out 4 (v) v out 5 (v) v out 6 (v) v out 7 (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 ?5 0 5 10 v out (v) time (s) v dd = 5v t a = 25c internal reference = 2.5v mi d s c a l e , g a i n = 2 mi d s c a l e , g a i n = 1 12664-050
data sheet ad5671r/ad5675r rev. b | page 17 of 32 figure 42 . digital - to - analog glitch impulse figure 43 . analog crosstalk figure 44 . dac - to - dac crosstalk figure 45 . 0.1 hz to 10 hz output noise plot figure 46 . noise spectral density (nsd) figure 47 . total harmonic distortion (thd) at 1 khz ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 15 16 17 18 19 20 21 22 v out (v) time (s) v dd = 5v gain = 1 t d = 25c reference = 2.5v code = 7fff to 8000 energy = 1.209376nv-s 12664-051 ?0.006 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0 2 4 6 8 10 12 14 16 18 20 v out (v) time (s) c h an n e l 1 c h an n e l 2 c h an n e l 3 c h an n e l 4 c h an n e l 5 c h an n e l 6 c h an n e l 7 12664-052 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 0.012 0 2 4 6 8 10 12 14 16 18 20 v out (v) time (s) c h a n n e l 1 c h a n n e l 2 c h a n n e l 3 c h a n n e l 4 c h a n n e l 5 c h a n n e l 6 c h a n n e l 7 12664-053 ch1 50.0mv m1.00s a ch1 401mv 2 1 12664-054 0 200 400 600 800 1000 1200 10 100 1k 10k 100k 1m nsd (nv/hz) frequenc y (hz) v dd = 5v t a = 2 5c ga in = 1 in t e r n a l r e f e r e n ce = 2 . 5 v f u l l s c a l e m i d s c a l e z e r o s c a l e 12664-055 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 4 6 8 10 12 14 16 18 20 thd (dbv) frequenc y (khz) v dd = 5v t a = 25c internal reference = 2.5v 12664-056
ad5671r/ad5675r data sheet rev. b | page 18 of 32 figure 48 . settling time vs. capacitive load figure 49 . settling time, 5.5 v figure 50 . hardware reset figure 51 . internal reference nsd vs. frequency figure 52 . internal reference voltage (v ref ) vs. temperature (a grade) figure 53 . internal reference voltage (v ref ) vs. temperature (b grade) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0.10 0. 1 1 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 time (ms) c l = 0 n f c l = 0. 1 n f c l = 1 n f c l = 4. 7 n f c l = 1 0 n f v out (v) 12664-057 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 v out (v) time (s) 12664-058 da c 1 da c 2 da c 3 da c 4 da c 5 da c 6 da c 7 da c 8 0 0.1 0.2 0.3 0 1 2 3 ?20 0 20 40 60 v out a t zs (v) v out a t ms (v) time (s) rese t mi d sc al e, g ai n = 1 z ero s c al e, g ai n = 1 12664-059 0 200 400 600 800 1000 1200 1400 1600 10 100 1k 10k 100k 1m interna l reference nsd (nv/hz) frequenc y (hz) v dd = 5v t a = 25c 12664-061 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 ?40 ?20 0 20 40 60 80 100 120 v ref (v) temper a ture (c) de v i c e 1 de v i c e 2 de v i c e 3 de v i c e 4 de v i c e 5 12664-062 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 ?40 ?20 0 20 40 60 80 100 120 temper a ture (c) de v i c e 1 de v i c e 2 de v i c e 3 de v i c e 4 de v i c e 5 v ref (v) 12664-063
data sheet ad5671r/ad5675r rev. b | page 19 of 32 figure 54 . internal reference voltage (v ref ) vs. load current and supply voltage (v dd ) figure 55 . internal reference voltage (v ref ) vs. supply voltage (v dd ) 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 2.5025 2.5030 2.5035 ?0.035 ?0.025 ?0.015 ?0.005 0.005 0.015 0.025 0.035 v ref (v) load current (a) v dd = 5v t a = 25c 12664-064 12664-065 v ref (v) v dd (v) 2.50010 2.50015 2.50020 2.50025 2.50030 2.50035 2.50040 2.50045 2.50050 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t a = 25c device1 device2 device3
ad5671r/ad5675r data sheet rev. b | page 20 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, fro m a straight line passing through the endpoints of the dac transfer function. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified di fferential nonlinearity of 1 lsb ma ximum ensures monotonicity. these dac s are guaranteed monotonic by design. zero - code error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. the ideal output is 0 v. the zero - code error is always positive because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is expressed in mv. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. the ideal output is v ref ? 1 lsb (gain = 1 ) or 2 v ref (gain = 2) . full - scale error is expressed in percent of full - scale range (% of fsr). gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. offset error drift offset error drift is a measurement of the change in offset error with a change in temperature. it is expressed in v/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured with code 256 loaded in the dac register. it can be negative or positive. dc power supply rejection ra tio (psrr) the dc power supply rejection ratio indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in mv/v. v ref is he ld at 2 v, and v dd is varied by 10%. output voltage settling time the output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input change. digital -to - analog glitch im pulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - sec, and is measured when the digital input code is change d by 1 lsb at the major carry transition (0x7fff to 0x8000). digital feedthrough digital feedthrou gh is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updat ed. it is specified in nv - sec, and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. noise spectral density noise spectral density is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. dc crosstalk dc crosstalk is the dc change in the output level of one dac in respo nse to a change i n the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impac t that a change in load current on one dac has on another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv - sec. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by first loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then, execute a software ldac and monitor the output of the dac whose digital code was not change d. the area of the glitch is expressed in nv - sec. dac -to - dac crosstalk dac - to - dac c rosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loadi ng the attack channel with a full - scale code change (all 0s to all 1s and vice versa ), using the write to and update commands while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv - sec.
data sheet ad5671r/ad5675r rev. b | page 21 of 32 multiplyi ng bandwidth the multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the dac . a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which t he output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement o f the harmonics present on the dac output. it is measured in db. voltage reference temperature coefficient (tc) voltage reference tc is a measure of the change in the reference output voltage with a change in temperature. the reference tc is calculat ed using the box method, which defines the tc as the maximum change in the reference output over a given tempera - ture range expressed in ppm/c , as follows: 6 ) ( ) ( ) ( 10 ? ? ? ? ? ? ? ? ? = temprange v v v tc nom ref min ref max ref ee v ref (max) is the maximum reference output measured over the total temperature range. v ref (min) is the minimum reference output measured over the total temperature range. v ref (nom) is the nominal reference output voltage, 2.5 v. temprange is the specified temperature range of ?40c to +125c.
ad5671r/ad5675r data sheet rev. b | page 22 of 32 theory of operation digital - to- analog converter ( dac ) the ad5671r / ad5675r are octal, 12- /16 - bit, serial input, voltage output dacs with an internal reference. the devices operate from supp ly voltages of 2.7 v to 5.5 v. data is written to the ad5671r / ad5675r in a 24 - bit word format via a 2 - wire serial interface. the ad5671r / ad5675r incorporate a power - on reset circuit to ensure that the dac output powers up to a known output state. the devices also have a software power - down mode that reduces the t ypical current consumption to 1 a. transfer function the internal reference i s on by default. gain is the gain of the output amplifier and is set to 1 by default. this can be set to 1 or 2 using the gain select pin (gain). when this pin is tied to gnd, all eight dac outputs have a span from 0 v to v ref . if this pin is tied to v logic , all eight dacs output a span of 0 v to 2 v ref . dac architecture the ad5671r / ad5675r implement segmented string dac architecture with an internal output buffer. figure 56 shows the internal block diagram. figure 56 . single dac channel architecture blo ck diagram the resistor string structure is shown in figure 57 . the code loaded to the dac register determines the node on the string where the voltage is tapped off and fed into the output amplifier. the voltage is tapped off by closing one of the switches and connecting the string to the amplifier. because each resistance in the string has same value, r, the string dac is guaranteed monotonic. figure 57 . resistor string structure internal reference t he ad5671r / ad5675r on - chip reference is enabled at power - up, but can be disabled via a write to the control register. see the internal reference and amplifier gain selection section for details. t he ad5671r / ad5675r ha ve a 2.5 v, 2 ppm/c reference , giving a full - scale output of 2.5 v or 5 v, depending on the state of the gain pin. the internal reference associated with the device is available at the v refout pin. this buffered reference is capable of dr iving external loads of up to 15 ma. output amplifiers the output buffer amplifier generates rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on the value of v ref , the gain pin, the offset error, and the gain error. the gain pin selects the gain of the output. if the gain pin is tied to gnd, all eight outputs have a gain of 1, and the output range is 0 v to v ref . if the gain pin is tied to v logic , all eight outputs have a gain of 2, and the output range is 0 v to 2 v ref . these amplifiers are capable of driving a load of 1 k? in parallel with 10 nf to gnd. the sle w rate is 0.8 v/s with a typical ? to ? scale settling time of 5 s. input register 2.5v ref dac register resistor string ref (+) ref (?) v ref v out x gnd gain (gain = 1 or 2) 12664-066 r r r r r to output amplifier v r e f 12664-067
data sheet ad5671r/ad5675r rev. b | page 23 of 32 serial interface the ad5671r / ad5675r use a 2-wire, i 2 c-compatible serial interface. these devices can be connected to an i 2 c bus as a slave device under the control of the master devices. the ad5671r / ad5675r support standard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10-bit addressing and general call addressing. input shift register the input shift register of the ad5671r / ad5675r is 24 bits wide. data is loaded msb first (db23), and the first four bits are the command bits, c3 to c0 (see table 9), followed by the 4-bit dac address bits, a3 to a0 (see table 10), and finally, the bit data-word. the data-word comprises 16-bit or 12-bit input code, followed by zero or four dont care bits for the ad5675r and ad5671r , respectively (see figure 58 and figure 59). these data bits are transferred to the input register on the 24 falling edges of scl. commands execute on individual dac channels, combined dac channels, or on all dacs, depending on the address bits selected. table 9. command definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n (dependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software reset (power-on reset) 0 1 1 1 internal reference and gain setup register 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 update all channels of input register simultaneously with the input data 1 0 1 1 update all channels of dac register and input register simultaneously with the input data 1 1 0 0 reserved 1 1 1 1 reserved table 10. address commands channel address[3:0] selected channel 1 a3 a2 a1 a0 0 0 0 0 dac 0 0 0 0 1 dac 1 0 0 1 0 dac 2 0 0 1 1 dac 3 0 1 0 0 dac 4 0 1 0 1 dac 5 0 1 1 0 dac 6 0 1 1 1 dac 7 1 any combination of dac channels can be selected using the address bits. figure 58. ad5675r input shift register content figure 59. ad5671r input shift register content db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command dac address dac data dac data command byte data high byte data low byte 12664-302 a3 a2 a1 a0 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command dac address dac data dac data command byte data high byte data low byte 12664-300
ad5671r/ad5675r data sheet rev. b | page 24 of 32 write and update com mands write to input register n (dependent on ldac ) command 0001 allows the user to write the dedicated input register of each dac individually. when ldac is low, the input register is transparent, if not controlled by the ldac mask register. update dac register n with co ntents of input register n command 0010 loads the dac registers and outputs with the contents of the input registers selected and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allows the user to write to the dac registers and updates the dac outputs directly. i 2 c slave address the ad5671r / ad5675 r have a 7 - bit i 2 c slave address. the five msbs are 00011 , and the two lsbs (a1 and a0) are set by the state of t he a1 and a0 address pins. the ability to make hardwired changes to a1 and a0 allows the user to incorporate up to four ad5671r / ad5675r devices on one bus (see table 11). table 11. device address selection a1 pin connection a0 pin connection a1 a0 gnd gnd 0 0 gnd v logic 0 1 v logic gnd 1 0 v logic v logic 1 1 serial operation the 2 - wire i 2 c serial bus protocol operates as follows: 1. the master initiates a data transfer by establishin g a start condition when a high to low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of th e 7 - bit slave address. 2. the slave device with the transmitted address responds by pulling sda low during the ninth clock pulse (this is called the acknowledge bit , or ack ). at this stage, all other devices on the bus remain idle while the selected device wa its for data to be written to or read from its input shift register. 3. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). transitions on the sda line must occur during the low period of scl; sda must remain stable during the high period of scl. 4. after all data bits are read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge (nack) for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse , and then high again during the 10 th clock pulse to establish a stop condition. w rite operation when writing to t he ad5671r / ad5675r , begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the ad5671r / ad5675r require two bytes of data for the dac , and a comm and byte that controls various dac func tions. three bytes of data must therefore be written to the dac with the command byte followed by the most significant data byte and the least significant data byte, as shown in figure 60. all these data bytes are acknowledged by the ad5671r / ad5675r . a stop condition follows. figure 60 . i 2 c write operation frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack by ad5671r/ad5675r ack by ad5671r/ad5675r sda r/w db23 a0 a1 1 0 0 0 1 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack by ad5671r/ad5675r ack by ad5671r/ad5675r frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 12664-303
data sheet ad5671r/ad5675r rev. b | page 25 of 32 read operation when reading data back from the ad5671r / ad5675r , begin with a s tart command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the address byte must be followed by the command byte, which determines both the read command tha t is to follow and the pointer address to read from; the command byte is also acknowledged by the dac. the user configures the channel to read back the contents of one or more dac input registers and sets the read back command to active using the command byte. then , the master establishes a repeated start condition, and the address is resent with r/ w = 1. this byte is acknowledged by the dac, indicating that it is prepared to transmit data. two bytes o f data are then read from the dac, as shown in figure 61. a nack condition from the master, followed by a stop condition, completes the read sequence. if more than on e dac is selected, dac 0 is read back by default. multiple dac readbac k sequence when reading data back from multiple ad5671r / ad5675r dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the address byte must be followed by the command byte, which is also acknowledged by the dac. the user selects the first channel to read back using the command byte. following this sequence , the master establishes a repeated start condition, and the address is resent with r/ w = 1. this byte is acknowledged by the dac, indicating that it is prepared to transmit data. the first two bytes of data are then read from dac input register n (selected using the command byte), msb first, as shown in figure 61 . the next two bytes read back are the contents of dac input register n + 1, and the next bytes read back are the contents of dac input register n + 2. data is read from the d ac input register s in this auto incremented fashion until a nack followed by a stop condition follows. if the content s of dac input register 7 are read out, the next two bytes of data read are the contents of dac input register 0 . figure 61 . i 2 c read operation frame 2 command byte frame 1 slave address 1 1 0 0 0 1 a1 a0 r/w db23 db22 db21 db20 db19 db18 db17 db16 9 9 1 start by master ack by ad5671r/ad5675r ack by ad5671r/ad5675r scl scl sda 1 9 9 1 1 9 9 1 ack by ad5671r/ad5675r repeated start by master ack by master frame 4 most significant data byte n frame 3 slave address ack by master nack by master stop by master frame 6 most significant data byte n + 1 frame 5 least significant data byte n 1 0 0 0 1 a1 a0 r/w db15 db14 db13 db12 db11 db10 db9 db8 sda scl (continued) sda (continued) db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 db10 db9 db8 12664-304
ad5671r/ad5675r data sheet rev. b | page 26 of 32 power - down operation the ad5671r / ad5675r contain two separate power - down modes. command 0100 is designated for the power - down function (see table 9 ). these power - down modes are software programmable by setting 16 bits, bit db15 to bit db0, in the input shift register. there are two bits associated with each dac chan nel. table 12 shows how the state of the two bits corresponds to the mode of operation of the device. any or all dacs (dac 0 to d ac 7 ) power down to the selected mode by setting the corresponding bits. see table 13 f or the contents of the input shift register during the power - down/ power - up operation. table 12 . modes of operation operating mode pd 1 pd 0 normal operation 0 0 power - down modes 1 k to gnd 0 1 tri s tate 1 1 when both bit pd1 and bit pd0 in the input shift register are set to 0, the device works normally with its normal power consumption of typically 1 ma at 5 v. however, for the two power - down modes, the supply current falls to typically 1 a. in addition to this fall, the output stage switches internally from the amplifier output to a resistor network of known values . this has the advantage that the output impedance of the devices are known while the devices are in power - down mode. there are two different power - down op tions. the output is connected internally to gnd through either a 1 k? resistor, or it is left open - circuited (tristate). the output stage is shown in figure 62. fi gure 62 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power - down mode is activated. however, the contents of the dac registers are unaffected in power - down mode, and the dac registers can be updated while the device is in power - down mode. the time required to exit power - down is typically 2.5 s for v dd = 5 v. load dac (hardware ldac pin) the ad5671r / ad5675r dacs have double buffered interfaces consisting of two banks of registers: input registers an d dac registe rs. the user can write to any combination of the input registers. updates to the dac registers are controlled by the ldac pin. instantaneous dac updating ( ldac held low) for instantaneous updating of the dacs, ldac is held low while data is clocked into the input register using command 0001. both the addressed input register and the dac register are updated on the 24 th clock, and the output changes immediately . deferred dac updating ( ldac is pulsed low) for deferred updating of the dacs, ldac is held high while data is clocked into the input register using command 0001. all dac outputs are asynchronously updated by pulling ldac low after the 24 th clock. the update occurs on the falling edge of ldac . figure 63 . simplified diagram of input loading circuitry for a single dac table 13 . 24 - bit input shift register contents of power - down/power - up operation [db23:db20] db19 [db18:db16] dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 [db15: b14] [db13: b12] [db11: b10] [db9:db8] [db7:db6] [db5:db4] [db3:db2] [db1:db0] 0100 0 xxx 1 [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] 1 x means dont care. resistor network v o u t dac power-down circuitry amplifier 12664-071 scl dac register interface logic amplifier ldac input register sda 12-/16-bit dac v out x v ref 12664-072
data sheet ad5671r/ad5675r rev. b | page 27 of 32 ldac mask register command 0101 is reserved for this software ldac function. the a ddress bits are ignored. writi ng to the dac using command 0101 loads the 8 - bit ldac register (db 7 to db0). th e default for each channel is 0, that is, the ldac pin works normally. setting the bits to 1 forces this dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin. this flexibility is useful in applications where the user wants to select which channels respond to the ldac pin. the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 15 ). setting the ldac bits (db0 to db 7 ) to 0 for a dac channel means that this channel update is c ontrolled by the hardware ldac pin. table 14. ldac overwrite definition load ldac register ldac bits (db 7 to db0) ldac pin ldac operation 0000 0000 1 or 0 determined by the ldac pin. 11111111 x 1 dac channels update and override the ldac pin. dac channels see ldac as 1. 1 x means dont care. table 15. write commands and ldac pin truth table 1 command description hardware ldac pin state input register contents dac register contents 0001 write to input register n (dependent on ldac ) v logic data update no change (no update) gnd 2 data update data update 0010 update dac register n with contents of input register n v logic no change updated with input register contents gnd no change updated with input register contents 0011 write to and update dac channel n v logic data update data update gnd data update data update 1 a high to low hardware ldac pin transition always updates the contents of the contents of the dac register with the contents of the input register on cha nnels that are not masked (blocked) by the ldac mask register. 2 when ldac is permanently tied low, the ldac mask bits are ignored.
ad5671r/ad5675r data sheet rev. b | page 28 of 32 hardware reset ( reset ) the reset pin is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user selectable via the rstsel pin. keep reset low for a minimum time (see table 5 ) to complete the operation . when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. while the reset pin is low, the outputs cannot be updated with a new value. a software executable reset function is also available that resets the dac to the power - on reset code. command 0110 is designated for this software reset function . any events on ld ac or reset during power - on reset are ignored. reset select pin (rs tsel) the ad5671r / ad5675r conta in a power - on reset circuit that controls the output voltage during power - up. by connecting the rstsel pin low, the output powers up to zero scale. note that this power - up is outside the linear region of the dac; by connecting the rstsel pin high, v out pow ers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. internal reference a nd a mplifier g ain s election the on - chip reference is on at power - up by default. to reduce the supply current, turn off this reference by setting the software programmable bit, db0, in the internal reference and gain setup register. the state of bit db2 in the i nternal reference and gain setup register determines t he output amplif i er gain setting for the lfcsp package (see table 16 and table 17 ). ign ore bit db2 for the tssop package . command 0111 is reserved for setting up the internal reference and amplifier gain . table 16 . internal reference and gain setup register bit description db2 amplifier gain setting db2 = 0; amplifier gain = 1 (default) db2 = 1; amplifier gain = 2 db1 reserved; set to 0 db0 internal reference db0 = 0; reference is on (default) db1 = 1; reference is off solder heat reflow as with all ic reference voltage circuits, the reference value experience s a shift induced by the soldering process. a nalog d evices, i nc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. the output voltage specification quoted previously includes the effect of thi s reliability test. figure 64 shows the effect of solder heat reflow (shr) as measured through the reliability test (precondition). figure 64 . solder heat reflow reference voltage shift l ong - term temperature d rift figure 65 shows the change in v ref value after 1000 h ou rs in the life test at 150 c. figure 65 . reference drift through to 1000 h ou rs 0 5 10 15 20 25 30 35 2.497 2.498 2.499 2.500 2.501 2.502 hits v ref (v) postsolder heat reflow presolder heat reflow 12664-073 60 70 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 0 h o u rs 168 h o ur s 500 h o ur s 1000 h o ur s hits v r e f (v) 12664-074
data sheet ad5671r/ad5675r rev. b | page 29 of 32 thermal hysteresis thermal h ysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold , to hot , and then back to ambient. thermal h ysteresis data is shown in figure 66 . it is measured by sweeping the temperature from ambient to ? 40c, then to + 12 5c , and returning to ambient. the v ref delt a is then measured between the two ambient measurements and shown in blue in figure 66 . the same temperature sweep and measurements were immediately repeated , and the results are shown in red in figure 66. figure 66 . thermal hysteresis table 17 . 24 - bit input shift register contents for internal reference and amplifier gain setup command 1 db23 (msb) db22 db21 db20 db19 db18 db17 db16 db1 t o db3 db2 db1 db0 (lsb) 0 1 1 1 x x x x x 1/0 0 1/0 command bits (c3 to c0) address bits (a3 to a0) dont care amplifier g ain reserved reference setup register 1 x means dont care. 0 1 2 3 ?130 ? 1 10 ?90 ?70 ?50 ?30 ?10 10 30 50 70 hits dis t ortion (ppm) first temperature sweep subsequent temperature sweeps 12664-075
ad5671r/ad5675r data sheet rev. b | page 30 of 32 applications informa tion power supply recomme ndations the ad5671r / ad5675r is typically powered by the following supplies: v dd = 3.3 v and v logic = 1.8 v. the adp7118 can be used to power the v dd pin. the adp160 can be used to power the v logic pin. this setup is shown in figure 67 . the adp7118 can operate from input voltages up to 20 v. the adp160 can operate from input voltages up to 5.5 v. figure 67 . low noise power solution for the ad5671r / ad5675r microprocessor inter facing microprocessor interfacing to the ad5671r / ad5675r is done via a serial bus that uses a standard protocol that is compatible with dsp processors and microcontrollers. the communications channel requires a 2 - wire interface consisting of a clock signal and a data signal. ad5671r / ad5675r to adsp- bf531 interface the i 2 c interface of the ad5671r / ad5675r is designed for easy connection to industry - standard dsp s and microcontrollers . figure 68 shows the ad5671r / ad5675r connected to the analog devic es, inc., blackfin? pro cessor. the blackfin processor has an integrated i 2 c port that can be connected directly to the i 2 c pins of the ad5671r / ad5675r . figure 68 . ad5671r / ad5675r to adsp - bf531 interface layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance . design the printed circuit board (pcb) on which the ad5671r / ad5675r are mounted so that the devices lie on the analog plane. the ad5671r / ad5675r must have ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitors are tantalum bead type. the 0.1 f capacitor must have low effective se ries resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where there are ma ny devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the gnd plane on the device can be increased (as shown in figure 69 ) to provide a natural heat sinking effect. figure 69 . pad connection to board galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier betwee n the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. i coupler? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5671r / ad5675r makes the devices ideal for isolated interfaces because the number o f interface lines is kept to a minimum. figure 70 shows a 2 - channel isolated interface to the ad5671r / ad5675r using an adum 1251 . for further information, visit www.analog.com/icoupler . figure 70 . isolated interface adp160 ldo adp7118 ldo 5v input 12664-176 1.8v: v logic 3.3v: v dd adsp-bf531 scl gpio1 ldac pf9 reset pf8 sda gpio2 ad5671r/ ad5675r 12664-077 ad5671r/ ad5675r gnd plane board 12664-078 decode sda controller ad u m 1251 1 scl 1 additional pins omitted for clarity. encode to scl to sda encode decode encode decode 12664-079
data sheet ad5671r/ad5675r rev. b | page 31 of 32 outline dimensions figure 71 . 20 - lead thin shrink smal l outline package [tssop] (ru - 20) dimensions shown in mill imeters figure 72 . 20 - lead lead frame chip scale package [lfcsp _wq ] 4 mm 4 mm body, very very thin quad (cp - 20 - 8) dimensions shown in millimeters ordering guide model 1 resolution temperature range accuracy reference temperature coefficient (ppm/c) package description package option ad5671rbruz 12 bits ?40c to +125c 1 lsb inl 2 (typical) 20- lead tssop ru -20 ad5671 rbruz - reel7 12 bits ?40c to +125c 1 lsb inl 2 (typical) 20- lead tssop ru -20 ad5671rbcpz - reel7 12 bits ?40c to +125c 1 lsb inl 2 (typical) 20- lead lfcsp_wq cp -20-8 ad5671rbcpz -rl 12 bits ?40c to +125c 1 lsb inl 2 (typical) 20- lead lfcsp_wq cp -20-8 ad5675raruz 16 bits ?40c to +125c 8 lsb inl 5 (typical) 20- lead tssop ru -20 ad5675 raruz - reel7 16 bits ?40c to +125c 8 lsb inl 5 (typical) 20- lead tssop ru -20 ad5675rbruz 16 bits ?40c to +125c 3 lsb inl 2 (typical) 20- lead tssop ru -20 ad5675rbruz - reel7 16 bits ?40c to +125c 3 lsb inl 2 (typical) 20- lead tssop ru -20 ad5675racpz - reel7 16 bits ?40c to +125c 8 lsb inl 5 (typical) 20- lead lfcsp_wq cp -20-8 ad5675racpz -rl 16 bits ?40c to +125c 8 lsb inl 5 (typical) 20- lead lfcsp_wq cp -20-8 ad5675rbcpz - reel7 16 bits ?40c to +125c 3 lsb inl 5 (typical) 20- lead lfcsp_wq cp -20-8 eval - ad5675rsdz ad5675r evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 020509-b bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 se a ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.75 2.60 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5
ad5671r/ad5675r data shee t rev. b | page 32 of 32 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12664 - 0 - 10/15(b)

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